Re: [oc] Xilinx block-RAM async read

[Richard Herveille <richard@asics.ws>]

Always use synchronous accesses for Xilinx and Altera memories. This 
effectively means a one-cycle write-access and a two-cycle read access for 
the memory.

Richard

>Dear All,
>
>I'm trying to port WishboneTK to Xilinx platform and I find myself agains
>the following problem: For WB read accesses should be asyncronous (am I
>right?) as clocked registers are on the reception side of the data-bus.
>However Xilinx block-RAMs (SpartanII but I think Vertex is the same in this
>manner) seems to support syncronous read only. Have anyone succeeded
>overcomming this?
>
>Best regards,
>Andras Tantos
>
>
>
>--
>To unsubscribe from cores mailing list please visit 
>http://www.opencores.org/mailinglists.shtml

--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml