Re: [oc] Xilinx block-RAM async read

[Damjan Lampret <lampret@opencores.org>]

Hi Andras,

you can delay acknowledge by one clock if you use Xilinx BlockRAMs.
However I have implemented a small controller that actually predicts
next address (of course this makes sense if accesses are sequential) and
thus you effectively can get almost the same performance as for async
memories (first access has one delay clock penalty). See this piece of
code in CVS under wb_prefetch_spram.

Again short answer to your question is just delay the acknowledge.

regards,
Damjan


Andras Tantos wrote:
> 
> Dear All,
> 
> I'm trying to port WishboneTK to Xilinx platform and I find myself agains
> the following problem: For WB read accesses should be asyncronous (am I
> right?) as clocked registers are on the reception side of the data-bus.
> However Xilinx block-RAMs (SpartanII but I think Vertex is the same in this
> manner) seems to support syncronous read only. Have anyone succeeded
> overcomming this?
> 
> Best regards,
> Andras Tantos
> 
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