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[oc] Xilinx block-RAM async read

To: <cores@opencores.org>
Subject: [oc] Xilinx block-RAM async read
From: "Andras Tantos" <andras_tantos@yahoo.com>
Date: Wed, 3 Oct 2001 21:32:33 +0200
References: <000201c14be0$fb307920$75e6b23f@oemcomputer>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

Dear All,

I'm trying to port WishboneTK to Xilinx platform and I find myself agains
the following problem: For WB read accesses should be asyncronous (am I
right?) as clocked registers are on the reception side of the data-bus.
However Xilinx block-RAMs (SpartanII but I think Vertex is the same in this
manner) seems to support syncronous read only. Have anyone succeeded
overcomming this?

Best regards,
Andras Tantos



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References:
- [oc] wide crc_32 doesn't need to be slow.
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