[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [oc] Xilinx block-RAM async read

To: <cores@opencores.org>
Subject: Re: [oc] Xilinx block-RAM async read
From: "Andras Tantos" <andras_tantos@yahoo.com>
Date: Thu, 4 Oct 2001 08:29:27 +0200
References: <000201c14be0$fb307920$75e6b23f@oemcomputer> <5.0.2.1.2.20011004060218.00aad4f8@asics.ws>
Reply-To: cores@opencores.org
Sender: owner-cores@opencores.org

Dear Richard,

> Always use synchronous accesses for Xilinx and Altera memories. This
> effectively means a one-cycle write-access and a two-cycle read access for
> the memory.

That's exactly what I was trying to avoid. BTW Altera can do asyncronous
reads.
Thanks anyway, it seems that there's no other solution.

Andras


--
To unsubscribe from cores mailing list please visit http://www.opencores.org/mailinglists.shtml

References:
- [oc] wide crc_32 doesn't need to be slow.
  - From: "llbutcher" <llbutcher@veriomail.com>
- Re: [oc] Xilinx block-RAM async read
  - From: Richard Herveille <richard@asics.ws>

Prev by Date: Re: [oc] wide crc_32 doesn't need to be slow.
Next by Date: Re: [oc] How to submit
Prev by thread: Re: [oc] Xilinx block-RAM async read
Next by thread: [oc] New project proposal
Index(es):
- Date
- Thread