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Re: [pci] about testbench
From
: cfk <cfk@pacbell.net>
[pci] CINEMA TONIGHT
From
: "CLIVE" <CliveJohnsan@hotmail.com>
[pci] about testbench
From
: random_user@163.com
Re: [pci] how to synthesize pci core
From
: saqib@and-or.com
[pci] Projects/Tenders in the Middle East
From
: MiddleEastBusiness@atozasia.com
Re: [pci] CardBus interface
From
: random_user@163.com
Re: [pci] CardBus interface
From
: "Chandrashekar" <chandrashekar@rassit.com>
RE: [pci] CardBus interface
From
: random_user@163.com
RE: [pci] CardBus interface
From
: "Charles Krinke" <ckrinke@pulselink.net>
Re: [pci] CardBus interface
From
: random_user@163.com
Re: [pci] CardBus interface
From
: "Chandrashekar" <chandrashekar@rassit.com>
Re: [pci] CardBus interface
From
: random_user@163.com
[pci] Can read config, cannot write config (yet)
From
: "Charles Krinke" <ckrinke@pulselink.net>
[pci] CardBus interface
From
: "Chandrashekar" <chandrashekar@rassit.com>
Re: [pci] CVS
From
: jskalany@globalstar.com.ar
Re: [pci] CVS
From
: jskalany@globalstar.com.ar
Re: [pci] BUS Mastering & TRDY generation ?
From
: "Dave Warren" <dave@luscher.co.uk>
Re: [pci] BUS Mastering & TRDY generation ?
From
: cfk <cfk@pacbell.net>
[pci] BUS Mastering & TRDY generation ?
From
: Gustaw47@poczta.onet.pl
Re: [pci] simulation
From
: Pinhas.Krengel@formalized.com
[pci] =?GB2312?B?0sa2r7mks8zKps34v6rNqMHLo6G7ttOttPO80rniwdk=?=
From
: "mobengcn" <mobengcn@yahoo.com>
[pci] simulation
From
: cfk <cfk@pacbell.net>
Re: [pci] bug in pci_behaviorial_master.v and system.v?
From
: "Miha Dolenc" <mihad@opencores.org>
[pci] bug in pci_behaviorial_master.v and system.v?
From
: sumnow <sumnow@263.sina.com>
[pci] Mail Delivery Status Notification
From
: Postmaster <Administrator@brainboxes.com>
RE: [pci] constrain file
From
: stevens@dtims.com
[pci] Mail Delivery Status Notification
From
: Postmaster <Administrator@brainboxes.com>
[pci] Mail Delivery Status Notification
From
: Postmaster <Administrator@brainboxes.com>
[pci] Mail Delivery Status Notification
From
: Postmaster <Administrator@brainboxes.com>
[pci] Mail Delivery Status Notification
From
: Postmaster <Administrator@brainboxes.com>
[pci] Mail Delivery Status Notification
From
: Postmaster <Administrator@brainboxes.com>
[pci] Mail Delivery Status Notification
From
: Postmaster <Administrator@brainboxes.com>
[pci] Mail Delivery Status Notification
From
: Postmaster <Administrator@brainboxes.com>
[pci] Mail Delivery Status Notification
From
: Postmaster <Administrator@brainboxes.com>
[pci] ncelab -MESSAGES
From
: pinhas.krengel@formalized.com
[pci] Mail Delivery Status Notification
From
: Postmaster <Administrator@brainboxes.com>
Re: [pci] constrain file
From
: cfk <cfk@pacbell.net>
Re: [pci] constrain file
From
: "Gvozden Marinkovic" <mgvozden@eunet.yu>
RE: [pci] constrain file
From
: "Tadej" <tadej@opencores.org>
Re: [pci] constrain file
From
: Pinhas.Krengel@formalized.com
[pci] How to synthesize the PCI bridge Core?
From
: "Xianyang Jiang" <xy_jiang@netease.com>
Re: [pci] PCI-Wishbone initialization
From
: "Dave Warren" <dave@luscher.co.uk>
Re: [pci] PCI-Wishbone initialization
From
: cfk <cfk@pacbell.net>
Re: [pci] PCI-Wishbone initialization
From
: "Dave Warren" <dave@luscher.co.uk>
[pci] PCI-Wishbone initialization
From
: cfk <cfk@pacbell.net>
[pci] constrain file
From
: "Gvozden Marinkovic" <gvozden@titan.etf.bg.ac.yu>
[pci] Re: PCI Addres Translation ?
From
: Andreas Bombe <bombe@informatik.tu-muenchen.de>
RE: [pci] RE: Implementation
From
: "Gvozden Marinkovic" <gvozden@saga.co.yu>
Re: [pci] RE: Implementation
From
: "Miha Dolenc" <mihad@opencores.org>
[pci] RE: Implementation
From
: "Gvozden Marinkovic" <gvozden@saga.co.yu>
Re: [pci] PCI Addres Translation ?
From
: cfk <cfk@pacbell.net>
[pci] PCI Addres Translation ?
From
: gustaw47@poczta.onet.pl
[pci] hierarchy of the design
From
: "PinhasNBeatris Krengel" <bknpk@hotmail.com>
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