Re: [ecc] My Viterbi Project and Problem(help)

[Nanda <nanda@cdotb.ernet.in>]

HI ,
THe design occupies so much of logic is becos of the REgister exchange
method . try using trace back method and the RAM inside the FPGA.U must
store the statemetric decision bits or survival path bits in the RAM
. this will also increase the speed , by the way what is ur traceback
depth ?

On Sat, 1 Dec 2001 malitj@263.net wrote:

> Hi ,
> I am a student. I have finished my viterbi 
> project:K=7;Rate=1/2,2/3,7/8;3 bit Soft ;f(max)=11MHz. but it is too 
> large (6464 Logic element in Altera's FPGA). I use Register Exchange 
> methde to implement Survivor Select and Update. So I used 64 ACS Unit.
> 
> How can I do better in the decreasing area of the viterbi decoder or 
> what is the problem of my decoder?
> 
> 
> Thanks!
> 
> Peter Ma
> 
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
K.G.Nanda Kumar
Senior Research Engineer
Satellite Communication
Centre for Development Of Telematics
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