[ecc] My Viterbi Project and Problem(help)

[malitj@263.net]

Hi ,
I am a student. I have finished my viterbi 
project:K=7;Rate=1/2,2/3,7/8;3 bit Soft ;f(max)=11MHz. but it is too 
large (6464 Logic element in Altera's FPGA). I use Register Exchange 
methde to implement Survivor Select and Update. So I used 64 ACS Unit.

How can I do better in the decreasing area of the viterbi decoder or 
what is the problem of my decoder?


Thanks!

Peter Ma

--
To unsubscribe from ecc mailing list please visit http://www.opencores.org/mailinglists.shtml