Re: [ecc] My Viterbi Project and Problem(help)

[Yu Yang <yu@okigrp.com.sg>]

64 个ACS显然太多,
在我做过的解码器中,
K=9,  RATE = 1/2,1/3, Traceback depth = 64,
4bit soft decoding,  symbol rate = 64k,
设计采用4M时钟,只用了4个ACS并行运算.
如果你 的设计速率要求不高的话,可以通
过增加运算次数来减少硬件.

希望对你有帮助

malitj@263.net wrote:

> Hi ,
> I am a student. I have finished my viterbi
> project:K=7;Rate=1/2,2/3,7/8;3 bit Soft ;f(max)=11MHz. but it is too
> large (6464 Logic element in Altera's FPGA). I use Register Exchange
> methde to implement Survivor Select and Update. So I used 64 ACS Unit.
>
> How can I do better in the decreasing area of the viterbi decoder or
> what is the problem of my decoder?
>
> Thanks!
>
> Peter Ma
>
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