Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[Tom Hawkins <tom1@launchbird.com>]

On Wednesday 28 May 2003 08:20 am, Marko Mlinar wrote:
>
> Tom,
>
> don't underestimate OO for synthesis. Although OO may seem
> unsuitable for RTL at first glance, but as a user of OO RTL
> language (for synthesis!) I can say with much confidence, that it
> is useful at least for:
> - memory block, different vendors, etc...
> - pads
> - cores
> - interfaces
> ...
>
> The OO defines an abstraction in different way than just defining
> 'interface' module as it is currently done in Verilog. For example
> you may define wishbone interface:
>
> wire[31:0] x = wishbone.read(address);
>
> where 'read' is a part of bus interface interface.

What is the behavior of the above?  I am interpreting this as, "A bus 
object 'wishbone' has a 'read' method that when given an 'address' 
performs a read operation and returns a result."

This implies that result is stored in some sort of register that is 
updated when the 'read' method is called.  But where and when is it 
valid to call 'read'?  Is this a continuous action, or can it only be 
invoked inside a synchronized always block?  What kind of logic can 
drive 'address'?  Is the following valid?

  x = wishbone0.read(wishbone1.read(address));

This feels like sequential software -- synthesis would have to 
generate an machine (aka, processor) to implement these sequential 
transactions.  Maybe I'm just having a hard time understanding how OO 
and RTL can work together.  I'd appreciate your input!  What language 
and tools are you using?

If your example is just another means to instantiate a bus reader, 
well then Confluence is OO too!

  X <- {Wishbone.Reader, WishboneBus Address, $}

Regards,
Tom


-- 
Tom Hawkins
Launchbird Design Systems, Inc.
952-200-3790
tom1@launchbird.com
http://www.launchbird.com/


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