Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Marco Antonio Simon Dal Poz <mdalpoz@lsi.usp.br>]

On 20 May 2003, Rudolf Usselmann wrote:

> > I'm new here. I see most of the projects are done in Verilog. Why Verilog?
> > Most school teach VHDL.... My university teach VHDL.
> > I really don't want to juggle two languages.
> 
> You should ask your school (and the other schools you are
> referring too), most of the industry is using Verilog.
> Search the archives, I have posted a message a while back
> in which the Synopsys CEO makes a statement that VHDL is
> dead. Which is probably not quite true, but shows you that
> the industry is at least trying to steer in to one direction ...

AFAIK, the industry is trying to steer in the direction of discarding
Synopsys. Please, correct me if I am wrong...

Best Wishes,

Marco Antonio

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