Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1

[Shehryar Shaheen <shehryar.shaheen@ul.ie>]

First I would like to say that I'm  a hardware engineer
 who can write that odd bit of software too and I don't
 have  nor would I like to have an associations with
 cheap SW designers ;-)

SystemC is more for system modeling (HW+SW) some
 complex SoCs like the E-GOLD GSM Chipset from Infenieon
 used SystemC in it's design process.

Siemens has also been using SystemC for ATM chipsets.

Sysnopys already has the CoCentric compiler for SysyemC synthesis
 and also at the DAC 2003 Synopsys would be showing up at the
 SystemC booth.

If you look at the RTL subset of SystemC you'll notice that it's very
similar
 to VHDL or Verilog RTL subset. So in terms of syhthesis people who don't
have
 experience with pure HDLs won't be able to just write some code in C++ and
 turn it into hardware.

But we'll probably see more executable specifications for SoCs being written
 in SystemC.


----- Original Message -----
From: "Joachim Strömbergson" <Joachim.Strombergson@InformAsic.com>
To: <cores@opencores.org>
Sent: Wednesday, May 21, 2003 7:56 AM
Subject: Re: [oc] Verilog coding style for Open Cores-RTL - Case in point
SHA1


Aloha!

Shehryar Shaheen wrote:
> Why would you say SystemC is a gonner ?!

* <rant> Because I belive it's based on a flawed concept of having cheap SW
designers writing code that magically transforms into real world HW</rant>

* Because the consumers (both companies, managers/tool buyers and fellow
engineers) says so:
[SNUG 2003 Trip Report]
http://deepchip.com/items/snug03-05.html

[DAC 2002 Trip Report]
http://www.deepchip.com/items/dac02-03.html

IMHO Superlog and SystemVerilog are taking the right approach. By evolving
Verilog to a language with better support for complex data types, efficient
verification, separate interfaces etc we can work with much more complex
designs. Yet, there is always a path back to RTL and generation of HW.

--
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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