Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Joachim Strömbergson<Joachim.Strombergson@InformAsic.com>]

Aloha!

Shehryar Shaheen wrote:
> Why would you say SystemC is a gonner ?!

* <rant> Because I belive it's based on a flawed concept of having cheap SW 
designers writing code that magically transforms into real world HW</rant>

* Because the consumers (both companies, managers/tool buyers and fellow 
engineers) says so:
[SNUG 2003 Trip Report]
http://deepchip.com/items/snug03-05.html

[DAC 2002 Trip Report]
http://www.deepchip.com/items/dac02-03.html

IMHO Superlog and SystemVerilog are taking the right approach. By evolving 
Verilog to a language with better support for complex data types, efficient 
verification, separate interfaces etc we can work with much more complex 
designs. Yet, there is always a path back to RTL and generation of HW.

-- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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