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Sorry,
I changed the code. eth_wishbone module is now reset in another way. I forgot to
update the test bench
to
properly reset this module. That's the reason simulation was not
ok.
Sorry
for inconvenience.
Regards,
Igor
-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of gwkim Sent: 3. maj 2002 2:24 To: ethmac@opencores.org Subject: [ethmac] RTL simulation
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