Re: [oc] Language

["Ryan Henderson" <hendersr@oit.edu>]

VHDL is loosely based off ADA.  I've never written any ADA, but I have
played with a little PL/SQL which is also based off ADA.  It's hauntingly
odd when a database language looks like an HDL.  I think VHDL is mid-80's.

Verilog isn't very old and is based off of C.  It's only recently become
widely used.  In my opinion verilog looks nice but does some pretty freaky
unpredictible stuff.  Maybe it's just the synthesizer, but I've seen it
genenerate some pretty different logic from code that should have the same
exact functionality.

    if a
        do b
    else
        do c

vs
    if !a
        do c
    else
        do b

these really should generate the same logic... I remember having some
problems with it using Verilog.

VHDL is more confusing... but better


that's my $0.02 on the matter
-Ryan


----- Original Message -----
From: "Agador Sparticus" <mega_gojira@wowmail.com>
To: <cores@opencores.org>
Sent: Wednesday, February 06, 2002 10:32 AM
Subject: [oc] Language


> In reading a lot of the project notes and questions going back and forth
I'm noticing that VHDL seems to be the language of choice. Is VHDL older
than verilog? I know good engineer should know both, but I've not yet
encountered a situation where I've needed to use my (limited) VHDL skills.
What's up?
>
>
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