Re: [oc] Language

[Billditt@aol.com]

VHDL was developed for systems modeling in 80's. Its syntax is based on ADA.
The US Govt, mainly dept of defense, pushed it. Lots of colleges used it for
defense dept. requirements on their research projects.
    Verilog was developed for modeling digital behaviour in 80's. Cadence 
bought
the company and pushed the language. Synopsys bought out their synthsesis tool
with Verilog support.

 For a long time, commercial companies
doing ASIC design favored Verilog, while colleges and defense contractors 
tended
toward VHDL. Also, Europeans and the Japanese tended toward VHDL.That is a 
generality, there are exceptions. For instance, TI standardized on VHDL. 

    Nowadays, it really doesnt matter. Synthesis tools support both, 
simulators
support both (even mixed designs). Usually, ASIC foundries bring out 
libraries in
Verilog first, but I havent heard of any problems from my friends using VHDL.

    I personally believe that SuperLog, the new product from the engineers who
developed Verilog, may eclipse VHDL. But that is only if SuperLog is accepted
widely, and VHDL isnt improved.

    ditt
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