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RE: [oc] Language



It's kind of like asking which apple is better, red or green? C or Pascal?
VHDL was created by committee some years before Verilog. VHDL is more
complex, but can do more. Verilog was written in the late 80s by, basically
one person. (Although it's now a formal IEEE thing.) From what I've seen in
my years of ASIC and FPGA development, VHDL seems to be used more by
government and military in the USA and also seems heavily used in Europe.
Verilog appears to be a more common choice for the private sector. However,
it depends on what you want to do. Both have good and bad. Using VHDL you
can do more "Spice" like things; specify loads, capacitance, lengths,
resistance. VHDL can also work to create mixed signal designs. The Verilog
working group has been playing with the idea of adding these sort of
extensions, but as of yet, Verilog mixed signal stuff is either absent or
not well supported. Many of the "Spice" like parameters are not directly
specified in the language either, but rather in SDF (timing) files and in
synthesis scripts and directives. All in all, I think it's a matter of
choice. Any fab I've ever worked with can accept both.

-rob.
 

> -----Original Message-----
> From: Agador Sparticus [mailto:mega_gojira@wowmail.com]
> Sent: Wednesday, February 06, 2002 11:33 AM
> To: cores@opencores.org
> Subject: [oc] Language
> 
> 
> In reading a lot of the project notes and questions going 
> back and forth I'm noticing that VHDL seems to be the 
> language of choice. Is VHDL older than verilog? I know good 
> engineer should know both, but I've not yet encountered a 
> situation where I've needed to use my (limited) VHDL skills. 
> What's up?
> 
> 
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