[oc] MAC FIR problem

[095204650580@ntu.edu.sg]

Hello,

I tried to do MAC (Multiplication and Accumulation) function using VHDL 
code to be implemented in FPGA. But I encountered some errors during 
its synthesis using Xilinx. Here is I attached the codes

--*********************
--* MULTIPLIER MODULE *
--*********************
--
--FILENAME: mul.vhd
--
--This is the VHDL source code for multiplier module
--pragma synthesis_on 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_MISC.ALL;

--library virtex;
--use virtex.components.all;
--library SYNOPSYS;
--use SYNOPSYS.ATTRIBUTES.all;
--library DWARE;
--use DWARE.BEHAVIORAL.all;

entity mul is

port(data: in integer range -32678 to 32767;
	CLK: in std_logic;
	reset: in std_logic;
	const: in integer range -256 to 255;
	start: in std_logic;
	output: out integer range -32768 to 32767);

end mul;

architecture M1 of mul is
	--attribute dont_unroll:boolean;

begin

process (CLK, reset)

	variable in16 : INTEGER range -32678 to 32767;
	variable inconst : INTEGER range -256 to 255;
	variable out25b: SIGNED (24 downto 0);
	variable out16b: SIGNED (15 downto 0);
	variable out25 : INTEGER range -16777216 to 16777215;
	variable out25_add : INTEGER range -16777216 to 16777215;
	--attribute dont_unroll of mul_loop:label is TRUE;

begin

--init variables and output ports

	reset_loop: loop

	out25b := "0000000000000000000000000";
	out16b := "0000000000000000";
	out25 := 0;
	out25_add := 0;
	in16 := 0;
	inconst := 0;
	output <= 0;

--RIsing edge of clock

	 if (CLK'event and CLK='1') then 
	if (reset='1') then exit reset_loop; end if;
	end if; --

	algorithm_loop:loop

--input handshaking protocol

	check_ready:loop
		if (start='1') then
			in16 := data;
			inconst := const;
			exit check_ready;
		end if;	

	
	if (CLK'event and CLK='1') then 
	if (reset='1') then exit reset_loop; end if;
	end if; 

	end loop check_ready;

	if (CLK'event and CLK='1') then 
	if (reset='1') then exit reset_loop; end if;
	end if; --

--multiplication and accumulation out in 25 bits

	mul_loop: for count in 0 to 20 loop
		out25_add :=  in16*inconst;
		out25:=out25 + out25_add;
		in16 := data;
inconst := const;
		
	--wait until clk'event and clk = '1';
	if (CLK'event and CLK='1') then 
	if (reset='1') then exit reset_loop; end if;
	end if; --

		end loop;


--rounding the final result by adding a LSB to the upper 16 bits if bit 8 is 
a '1'

	out25b := conv_signed(out25,25);
	if (out25b(8)='1') then out25b := out25b + 512; end if;

--converting the final results to 16 bits by discarding the lower 9 bits 
and output the fila result to the output port

	out16b:= out25b(24 downto 9);
	output <= conv_integer(out16b);

--initialize the variable that is used to hold the final sum of FIR filter 
operation 

	out25:=0;

	--wait until clk'event and clk = '1';
	if (CLK'event and CLK='1') then 
	if (reset='1') then exit reset_loop; end if;
	end if; --

   end loop algorithm_loop;

  end loop reset_loop;

 end process ;

end M1;
--
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