[pci] PCI bursts

[Daniel Hedberg <daniel@gaisler.com>]

Hi,

I have trouble making the pci core to issue block reads on the pci bus 
as pci initiator. The framen signal only goes low for one cycle (single 
transfer).
I simulate two pci cores in my pci test bench in which they target each 
other with consecutive address bursts. I have enabled pref_en and mrl_en 
in w_img_ctrlX as stated on page 23 in rev 0.6 of pci_specification and 
the w_baX bit0 is set to MEM space.
Is there an obligation of transfer type issued on the Wishbone bus to 
get a burst on PCI? I use the CAB signal to issue double word transfers.

I only have this problem when issuing read. Write propagate smoothly.

Could anyone in detail explain how the CAB signal is used. It is not 
described very thoroughly I drive it high when I issue STB and keep it 
there until the (second) STB is acknowledged.

I also have a question about conf_space.v ~row: 1000
Shouldn't something like this be added for every Image or image reads 
will not return prefetchable bit?

->            w_conf_data_out[3] = pci_img_ctrl1[1] & pci_am1[31] & 
~pci_ba1[0]; //DANIEL


---
begin
    case (w_conf_address_in[8])
    1'b0 :
    begin
      case ({w_conf_address_in[7], w_conf_address_in[6]})
      2'b00 :
      begin
        // PCI header - configuration space
        case (w_conf_address_in[5:2])
        4'h0:
        begin
            w_conf_data_out = { r_device_id, r_vendor_id } ;
            w_reg_select_dec = 56'h00_0000_0000_0000 ; // Read-Only register
        end
        4'h1: // w_reg_select_dec bit 0
        begin
            w_conf_data_out = { status_bit15_11, r_status_bit10_9, 
status_bit8, r_status_bit7, 1'h0, r_status_bit5,
                                 5'h00, 7'h00, command_bit8, 1'h0, 
command_bit6, 3'h0, command_bit2_0 } ;
            w_reg_select_dec = 56'h00_0000_0000_0001 ;
        end
        4'h2:
        begin
            w_conf_data_out = { r_class_code, r_revision_id } ;
            w_reg_select_dec = 56'h00_0000_0000_0000 ; // Read-Only register
        end
        4'h3: // w_reg_select_dec bit 1
        begin
            w_conf_data_out = { 8'h00, r_header_type, latency_timer, 
cache_line_size_reg } ;
            w_reg_select_dec = 56'h00_0000_0000_0002 ;
        end
        4'h4: // w_reg_select_dec bit 4
        begin
            w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = 
pci_ba0_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
                                                                
 pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
            w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
            w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
            w_reg_select_dec = 56'h00_0000_0000_0010 ; // The same for 
another address
        end
        4'h5: // w_reg_select_dec bit 8
        begin
            w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = 
pci_ba1_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
                                                                
 pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
            w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
            w_conf_data_out[3] = pci_img_ctrl1[1] & pci_am1[31] & 
~pci_ba1[0]; //DANIEL
            w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
            w_reg_select_dec = 56'h00_0000_0000_0100 ; // The same for 
another address
        end
        4'h6: // w_reg_select_dec bit 12
        begin
            w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = 
pci_ba2_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
                                                                
 pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
            w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
            w_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
            w_reg_select_dec = 56'h00_0000_0000_1000 ; // The same for 
another address
        end
        4'h7: // w_reg_select_dec bit 16
        begin
            w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = 
pci_ba3_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
                                                                
 pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
            w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
            w_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
            w_reg_select_dec = 56'h00_0000_0001_0000 ; // The same for 
another address
        end
        4'h8: // w_reg_select_dec bit 20
        begin
            w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = 
pci_ba4_bit31_12[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] &
                                                                
 pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
            w_conf_data_out[(3
---


Best regards,
Daniel

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