[pci] Re: pci-digest V1 #41

["llbutcher" <llbutcher@veriomail.com>]

I continue working on the PCI_Blue_Interface.
I will drop a new version of the code soon.

The Master and Target are tied together, so it does not seem
simple to break the design into pieces, to allow parallel
development.  I sort of want to do them myself.

Once something is working, the change from 32 bit to 64
bit COULD be done in several pieces.

The PCI_Blue_Interface is not wishbone-aware.  It should be
easy to do a parallel effort to make a wishbone wrapper.


I hope to be finished by the end of the July 4'th week.

Unfortunately, I had hoped to be finished by LAST July too.
So everyone should keep working on all fronts.

I invite people to look at the pci_blue_interface, which has a somewhat
working behaviorial PCI bus test environment written in verilog.

Is anyone interested in working with Vera?

Blue Beaver

>----------------------------------------------------------------------
>From: "Miha Dolenc" <mihad@opencores.org>
>Date: Mon, 4 Jun 2001 10:52:48 +0200
>Subject: [pci] Status
>
>Hello everyone!
>
>    I just wanted to ask everybody if they are working on some part of the
>bridge already and if they do, how far did they come with it.
>    And if anybody new is interested in bridge design, please post a
message
>with your interest to the pci mailing list.
>
>Regards,
>    Miha Dolenc
>