Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Rudolf Usselmann <rudi@asics.ws>]

On Wed, 2003-05-28 at 02:20, Tom Hawkins wrote:
> On Tuesday 27 May 2003 11:58 am, Shehryar Shaheen wrote:
> > So what would Sytem Verilog have in the offing that
> >  SystemC doesn't ?
> >
> > Would you think that the reason that SystemC is not popular is
> >  cause the learning curve associated with a new language tends
> >  to put off many users who already have a firm grip over current
> >  HDLs ?
> 
> SystemC is not popular because C, object-orientation, and imperative 
> programming are very poor languages and paradigms for describing 
> hardware systems.


I have to disagree here, Tom. It's not the Object Oriented aspect
that make a language like SystemC dis-liked by most HW designers.
Matter of fact, Object Oriented languages are quite popular, look
at Vera and E.
In my opinion the reason SystemC is dead (and I did try it several
times) is because it is a "Software Development" language. By default
the flow of the program is sequential. I find it very difficult to
think and write hardware descriptions (even behavioral) that are
equivalent to an 'alway' or 'assign' statements in verilog. Both
of these are constantly executed in parallel. Well, virtually in
parallel. The time is advanced after all of these 'always' and assign'
blocks have been executed. I don't have to think about time advancing
and parallelism when writing HDL. It's like drawing gates but on a
higher level.
This in my opinion is why SystemC is dead. I have written quite a bit
C and C++ code, and feel that I know both of those languages fairly
well.

> It is certainly not the learning curve.  In fact, most HW engineers 
> are already masters of C, not to mention Perl, Python, Ruby, etc.
> 
> RTL designers live and breath dataflow, hierarchy, and component-based 
> design methodologies -- this is part of the reason why HW engineers 
> are better software developers than most software developers.

Hmm, I should try writing software for a living ! ;*)

> Unfortunately, SystemVerilog adds a lot of useless S/W baggage as 
> well: classes, unions, a slew of C datatypes, forks/joins, 
> semaphores, mailboxes.  Why did the SW guys controlling the standards

Actually I like those things ! Specially Mailboxes ! Ever try to
verify a 20 port Gigabit switch ? Good Luck !

Honestly, i don't know enough about all the feature SystemVerilog
is adding. BUT, I'm thinking if it does build on Verilog, whats
there to loose ? Guys who don't like all the new constructs, can
stay in their comfort box and only use the part of the language
they feel comfortable with. The rest of us, more adventurous guys,
will love the additional help we get from the additions ...

> committee feel the urge to add these features to Verilog?  Answer: 
> Because 95% of all SW guys have never experienced anything outside 
> C++ or Java -- arguably the 2 worse programming languages on the 
> planet.   
> 
> But, of course, I'm biased. :-)  I only designed Confluence because 
> choosing between Verilog and VHDL is picking a lesser of two evils,
> and SystemC, Handel-C, et al, was a big step backwards.
> 
> -Tom

Regards,
rudi               
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