Re: [oc] synthesize and pipeline programming

["Andras Tantos" <andras_tantos@yahoo.com>]

Hi!

> 2) If I am trying to do the formal verification,
> assume that I have already have the synthesized
> netlist based on certain vendor 's library using the
> synthesize tool, Design Compiler, how can I feed the
> netlist into the HDL simulator, get the simulation
> result and then compare with the non-synthesized
> simulation results? I guess my question is : Can the
> HDL simulator recognize the library cells?

I guess I can answer this, at least if your target technology is FPGA. Most
vendors supply primitive-libraries for simulators. They make sure that their
synthetizer will emit references to those library elements if you create a
gate-level verilog or VHDL output. Take xilinx for example: their
primitive-ligrary is called simprim. At the end of the synthesizys process
you use two utilities to generate a gate-level VHDL output (probably verilog
too, but I use VHDL):
ngdanno - will put back signal names and other annotation info into the ngd
file
ngd2vhdl - will that file into a VHDL source. (ngd2ver is the verilog
counterpart tool)

At the end of the process you'll get a module with the same interface as
your original top-level module but with a different architecture, containing
gate-level RTL code. You will also get along the synthesis process an sdf
file containing timing information.

You feed one or both of those files back to your simulation tool and can
exercise it under the exact same test-bench you tested your pre-synthesis
implementation. Many tools, like Active HDL or ModelSIM has the capability
to compare the resulted wave-forms to each other.

Good luck,
Andras Tantos


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