Re: [oc] synthesize and pipeline programming

[Madhusudhan Rao <madhu_sudhana_rao@yahoo.com>]

Hai Jay,
    1. If you want to better optimization in your
pipeline case better to synthesize as single module.
If u synthesize individually Design Compiler will take
care about individual stage optimigation only.

    2. HDL simulator can recognize library
information.
you need to supply standard delay format file by using

$sdfannotate.
   
    I hope the above info will solve your problem.

Regards
madhu


--- jae lim <jlim0011@yahoo.com> wrote:
> Hello Everyone
> 
> My name is Jay and I am recently working on some
> RISC
> processor verilog Coding. I have some questions, if
> your guys could help me out, I will be more than
> thank
> you...
> 
> 1) For the pipelined Simple RISC processor, is it
> easier for the synthesis tool to optimize the code
> if
> I implemented as five stage pipeline as small
> modules
> as possible or it doesn't matter even if I implement
> it as a whole big module? If the former is the case,
> should I divide the module as five stages, including
> every functional units into the stage modules or
> should I put the functional units as individual
> modules?
> 
> 2) If I am trying to do the formal verification,
> assume that I have already have the synthesized
> netlist based on certain vendor 's library using the
> synthesize tool, Design Compiler, how can I feed the
> netlist into the HDL simulator, get the simulation
> result and then compare with the non-synthesized
> simulation results? I guess my question is : Can the
> HDL simulator recognize the library cells?
> 
> Any suggestions will be greatly helpful!!
> 
> Have a nice weekend.
> 
> Jay
> 
> 
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=====
MadhusudhanaRao.M

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