Modules of Tx Ethernet MAC :
1. FIFO Synchronization
The function of this module is to keep synchronization all outputs with the rising edge of input clock. FIFO will transmit a valid data nibble output if transmit_enable is asserted. When transmit_enable is asserted, tx_en will be asserted. If transmit_error is asserted tx_er will be asserted too.
2. IFG Timer
The function of this module is to assure time interval between two
packets of data or Inter Frame Gap (IFG) is 96 bit time or 24 clock
cycles. In half duplex mode, if counter can pass IFG without any
crs signal, transmit_available_p will be asserted. After asserting
transmit_available_p pulse, this module will monitor carrier signal
again. When operates in full duplex mode, this module will ignore
any crs signals and will count IFG after transmit_enable has been
disappeared.
The IFG has two intervals time, IFG_1 for the first 60 bit times
and IFG_2 for the following 36 bit times of IFG. If crs signal
appears in the IFG_1 then the value of counter is reseted. But, if
the crs signal appears in the IFG_2 then the counter will keep
running until 96 bit times has been passed. This operation makes
every station has an equal opportunity to access the medium.
3. Defer Counter
The function of this module is to limit defer time for waiting opportunity to transmit a packet of data. If transmit_new_p pulse is asserted, that indicates a new packet is ready to be transmitted, then counter start counting. When the counter has reached the maximum value of defer time, excess_deferral will be asserted until transmit_new_p appears again. Thus, the defer counter will be reseted when transmit_new_p is asserted and will stop counting when transmit_available_p is asserted. The maximum value of defer time is 2 times of the maximum length of Ethernet frame, that is 3036 byte or 6072 clock cycles.
4. Frame Length Counter
The function of this module is to count the length of frame has been
transmitted to MII.
The length counter counts the length of frame while transmit_enable
is detected and will be reseted if transmit_enable is not asserted.
If transmit_data_end is detected, the FCS counter will start
counting.
This module also detects excessive length and condition when data
has been transmitted is 64 byte. Note, that the length counter
counts Preamble and SFD at the beginning of operation, which makes
the maximum length of frame and 64 byte indicator increased by 16.
5. Collision Counter
The functions of this module are to count collision events, inspect
number of consecutive collisions, and detect late collision. If
collision appears while transmit_enable is asserted and coll_event_p
is asserted. Then, the value of counter is increamented.
But, if collision is detected while Tx Eth MAC transmits Preamble or
SFD, coll_event_p will be activated after all Preamble and SFD
patterns have been transmitted. If collision is detected when the
value of counter is 15, then excessive_coll is asserted and will be
deasserted when a new packet comes.
If collision is detected when transmit_64byte has been asserted by
Frame Length Counter, late collision occurs.
When operates in full duplex mode, this module ignores any collision
signals.
6. Random Number Generator
This module generates random number using Linear Feedback Shift Register which contains 10 bit register. This Random Number Generator will select random number from range between 0 to (2k)-1 with k is the smaller number between number of collision and 10. The number of collision is equal to coll_attempt.
7. Backoff Timer
The function of this module is to determine interval time for backoff operation after a start_backoff is detected. This interval time is calculated from multiplication between random number and slot time, that is random x 128 clock cycles. This module takes random number from Random Number Generator when start_backoff is detected.
8. Jam Timer
The function of this module is to determine how long JAM pattern has been transmitted after a collision.
9. CRC Generator
The function of this module is to generate CRC number, which will be added to Ethernet frame as FCS field. The CRC number is calculated from Destination Address field till Data field, includes PAD bits if exists, and will be computed while compute_crc is enabled. The Paralel CRC Algorithm is used to calculate CRC number, and CRC is calculated from 4 bits of data every one clock cycle.
10. Data Multiplexer
The function of this module is to determine which data nibbles will be transmitted to MII, which are related to data_select signal from state machine. Data nibble 4'b0101 is pattern for Preamble, JAM, and PAD. While data nibble 4'b1101 is pattern for SFD.
11. Tx State Machine
The function of this module is to control transmit process.
When host has packet of data to be transmitted, tx_sof will be
activated. Then, the State Machine will give transmit_new_p signal
to restart Defer Counter and Collision Counter and wait until
transmit_available_p from IFG Timer is detected to get opportunity
to transmit Preamble and SFD. When waiting transmit_available_p, the
State Machine monitors excess_deferral to limit waiting time for
transmit operation.
After IFG has passed and transmit operation has got opportunity,
the State Machine will give appropriate data_select signal to Data
Multiplexer and assert transmit_enable to FIFO Synchronization,
Collision Counter, Frame Length Counter, and IFG Timer. The State
Machine will also give transmit_preamble to Collision Counter
followed by transmit_sfd.
The Preamble Field will be transmitted if the transmit_available_p
is detected until the next 15 clock cycles then SFD Field will be
transmitted for one clock cycle. The Data Field will be transmitted
if the value of count_length is greater then 16 until tx_eof is
detected. But, the PAD pattern will be transmitted if tx_eof is
detected when the value of count_length is less than 136, which is
the minimum length of Data field added by Preamble and SFD Field,
and will be deactivated if the value of count_length reaches 136.
The FCS field will be transmitted if tx_eof is detected and the
value of count_length is greater than or equal to 136.
If Data Field starts to be transmitted, tx_data_used and compute_crc
are asserted. Then, the State Machine will monitor tx_eof that
indicates the last nibble of data is placed in tx_data.
If tx_eof is detected active and Tx Eth MAC doesn't have to send PAD
pattern, the State Machine will give transmit_fcs to Frame Length
Counter and deassert compute_crc signal.
While transmit operation is running, the State Machine monitors
tx_underrun, coll_event_p, and excessive_length continuously.
If detected, transmit operation will be aborted or dropped. If
coll_event_p is detected, the State Machine will give tx_retransmit
and start_backoff pulse signal, and deasserts transmit_enable,
compute_crc, and tx_data_used. The following operation is waiting
backoff_p and then asserts transmit_enable again to restart transmit
operation from the beginning of Preamble Field or abort transmission
because late collision and or excessive collision is detected.
If transmit operation terminates in normal condition or because any
error conditions, the State Machine will deassert transmit_enable
and followed by status signal.
written by: Novan H