Block Diagram of Tx Ethernet MAC :

Brief Description :

TxEthMAC implements CSMA/CD protocol when transmiting packets of data. Before transmiting packets of data, TxEthMAC must assure that medium is idle and then monitors medium continuously if there is a collision in the middle of transmit process. If collision happened, TxEthMAC makes backoff operation and retries to transmit after a random period depends on number of collision attempt. The transmit process can be aborted or dropped if one of the following conditions is detected :

• excess deferral, occurs when TxEthMAC can't get opportunity to transmit longer than twice maximum length of Ethernet frame
• late collision, occurs when collision is detected after 512 bits of data has been transmited
• excessive collision, occurs when collision is detected more than 15 times
• underrun, occurs when host can't provide nibbles of data for transmit operation
• excessive length, occurs when the length of packet is longer than 1518 bytes

Clock is provided by MII through tx_clk, which frequency is 2.5 MHz when operates at 10 Mbps and 25 MHz when operates at 100 Mbps.

TxEthMAC consists of eleven modules :

• FIFO Synchronization
• IFG Timer
• Defer Counter
• Frame Length Counter
• Collision Counter
• Random Number Generator
• Backoff Timer
• Jam Timer
• CRC Generator
• Data Multiplexer
• Tx State Machine

Behavioral model in Verilog can be downloaded from here (January 12, 2001).

This model can be synthesized and implemented using Xilinx Foundation Series 1.5 with target device Xilinx XCV50 speed grade -5 succesfully.

Modules of Tx Eth MAC

Eth MAC

written by: Novan H