Signal Descriptions
| Signal | Type | Description |
|---|---|---|
| rx_dv | in | rx_data available on MII and is being sent to MAC |
| rx_data [3:0] | in | data (nibble) transferred from MII when rx_dv active |
| rx_error | in | media error was detected in the frame presently being transferred to MAC |
| data [3:0] | out | data (nibble) transferred from rx_buffer to FIFO |
| data_valid | out | data is available on rx_buffer and is being sent from rx_buffer to FIFO |
| last_data | out | a single clock signal indicates the last nibble transferred from buffer to FIFO |
| rx_status [15:0] | out | contains the receive status of receive frame |
| rx_status_valid_n | out | a single clock signal indicates the receive frame status signals are valid |
| eth_address | in | ethernet address (48 bits) |
| rx_clk | in | clock signals from MII |
| reset_n | in | active low signals that initializes the receive MAC function |
| Status signal | Description |
|---|---|
| rx_status[0] | 1 : rx_error detected or max. length of frame is exceeded, else = 0 |
| rx_status[1] | 1 : destination address is matched, else = 0 |
| rx_status[2] | 1 : destination address is multicast or broadcast, else = 0 |
| rx_status[3] | 1 : no CRC error, else = 0; error |
| rx_status[15:4] | length of decapsulated frame (in nibble) |
Brief Description :
The Rx Ethernet MAC block is responsible for receiving data and implements
CSMA/CD protocol. The receive process can be aborted or dropped if one of
the following conditions is detected :
Clock is provided by MII through rx_clk, which frequency is 2.5 MHz when operates at 10 Mbps and 25 MHz when operates at 100 Mbps.
Rx Ethernet MAC consists of five modules :
Rx Ethernet MAC code in Verilog (Feb 12, 2001)
written by: Mahmud G