Re: [pci] TOP.v to TOP.sch

[Matt Schulte <matts@commtech-fastcom.com>]

Does anyone know if Xilinx's ISE will let you do this?  Can I write a vhdl 
module, turn it into a package and then connect it up to the verilog pci 
project?

----- Original Message ----- 
From: Marco Buffa <marcobuffa@l... > 
To: pci@o...  
Date: Mon, 17 Jun 2002 16:55:02 +0100 
Subject: Re: [pci] TOP.v to TOP.sch 

> 
> 
> Nico Weling ha scritto: 
> > This will successfully synthesize but the card is not be seen 
> by the system (lspci)! 
> > What did I wrong??? 
> FPGA Express works with mixed (VHDL and verilog) projects :-) 
> 
> You can create your own part in VHDL and connect it to the core 
> with a 
> hierarchical block written in VHDL... 
> I confirm it works very well. 
> 
> I don't like schematics: I can't see what I'm really doing :-( 
> 
> Regards. 
> -- 
> Marco (Politecnico di Milano, Italy) 
> 
> "Qui se accendessero le luci e riabbassassero le luci 
> ci troverebbero tutti in piedi con gli occhi aperti, qui" 
> (Ivano Fossati, "Sigonella") 
> 
--
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