RE: [pci] TOP.v to TOP.sch

[Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>]

>>>>> "Nico" == Nico Weling <eedniwe@eed.ericsson.se> writes:

    Nico> Hi Matt,
    >> I am in exactly the same situation, I only know VHDL not Verilog.  Is
    >> there any way you could tell me how you have gotten as far as you
    >> have.  I am having trouble even getting the project put together.

I assume you are using 5.2. in 5.1 the feature of multiple include/library
pathes was broken.

    Nico> Copy ise-openpci.npl (provided by Uwe) to
    Nico> /pci/apps/crt/syn/webpack/

    Nico> Manually add all source files from /pci/apps/crt/rtl/verilog/
    Nico> /pci/rtl/verilog/ expcept the TOP.v to the project

No need to manually add the files. Include/Library pathes should cares for
that. Can you try to help me find out whats wrong? First in
"Edit->Preferences->Processes" select "Advanced". The under with TOP
selected in "Sources in Procet:" Select "Synthesis->Properities" in
Processes in Current Source" . Under "Synthesis Options" check the entries
for "Verilog Search Path" and "Verilog Include Directories".
They both should contain "..\..\rtl\verilog ..\..\..\..\rtl\verilog"

On the console, "cd" to the "pci/apps/crt/syn/webpack" directory. Do a "dir
..\..\rtl\verilog" and "dir ..\..\..\..\rtl\verilog". Both  dir commands
should show the appropriate content.

If everything seems right so long, but the files still aren't found, try to
change Verilog Search Path" and "Verilog Include Directories" to
"../../rtl/verilog ../../../../rtl/verilog". I work with Webpack-5.2 under
wine, maybe wine is more tolerant with the slashes.

Bye

Bye

	
    Nico> Copy pci_constants.v pci_user_constants.v bus_commands.v
    Nico> ssvga_defines.v to /pci/apps/crt/syn/webpack/
     
    Nico> Now the project should compile without errors.

    >> I am using a Spartan-II development board

    Nico> I'm using a selfmade PCI-board but the PCI part it is similar to
    Nico> the MEMEC Spartan-II development board.

    >> ...and I would also like to attach something simple to the WB bus so
    >> that I can see if I can make it work.

    Nico> This I didn't succeed yet. As soon as something works I let you
    Nico> know.


    Nico> Regards,

    Nico> Nico.

    Nico> -- To unsubscribe from pci mailing list please visit
    Nico> http://www.opencores.org/mailinglists.shtml

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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