Re: [pci] HOST vs GUEST

["Miha Dolenc" <mihad@opencores.org>]

I'm sorry if the design document isn't clear enough. I will take a look at
it and update it if necessary! The mentioned RO constraints only apply for
configuration space accesses. So if GUEST, you will need other PCI masters
to configure the bridge, if HOST,  WB Master is responsible for bridge
configuration. So for your application, GUEST will be the right choice.
Basic operation is the same for both HOST and GUEST.
And to answer your previous question:
system.v also includes user constants, so you cannot run guest simulation
for host bridge. The difference between simulations is in conf. space
accesses and interrupt generation testcases. Some additional features are
also tested when bridge is defined as HOST ( like configuration and
interrupt acknowledge cycle generation ). Everything else (reads/writes,
transaction ordering etc) is the same for both kinds.

Regards,
Miha Dolenc


----- Original Message -----
From: "cfk" <cfk@pacbell.net>
To: <pci@opencores.org>
Sent: Sunday, May 19, 2002 10:38 AM
Subject: [pci] HOST vs GUEST


> Since I don't seem to yet grok the HOST vs GUEST concept in the PCI Bridge
> Core, I went back this morning and read the "PCI IP Core Design Document"
> more carefully. When I get to paragraph 2.3.1, I see two mutually
exclusive
> statements. The first one says: 'If the PCI bridge is implemented as HOST,
> then RW is provided for WB acesses, but RO for PCI accesses". The second
one
> says "If the PCI bridge is implemented as GUEST then RW is provided for
PCI
> target unit and RO for WB accesses".
>
> Maybe I am getting caught up in semantics a bit here. What I need to be
able
> to do is perform RW to both sides of the bridge. I can accept some
> constraints on either timing, mutual exclusivity, or addresses. Basically,
I
> need to be able to perceive the PCI bridge as a way to read and write(RW)
> from the PCI bus it is connected to and have those reads and writes
> translated into reads and writes on the WB bus to some other WB compatible
> core (lets pick the gpio as the simplest one for now). Similarly, I need
to
> be able to have the WB side of this same core accept some asychronous
event
> (as described in the gpio core, for instance) and have that event
translate
> back into some memory write to the PCI bridge on the WB side and become a
> memory write on the PCI device where the PCI bridge acts as a bus master
> long enough to request the bus from the yet to be created arbiter and
write
> 1 or more memory locations.
>
> So, my question is, "Am I perceiving the capability of the PCI bridge core
> correctly or incorrectly and am I getting too hung up on HOST versus GUEST
> semantics in the PCI IP Core Design Document?
>
> Charles Krinke
>
>
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