Re: [pci] first day with Modelsim

[cfk <cfk@pacbell.net>]

Dear Bill:
    I will try the commenting in system.v out the transaction_ordering (line
862) and target_completion_expiration (line 864-866) tasks and display
statements today along with redefining some of my constants in
pci_user_constants.v. I am hoping that I can keep FPGA and XILINX commented
out for the simulation, but will change my bridge from GUEST to HOST.

    That actually brings up a couple of questions. The first is "What do we
mean to run a GUEST simulation to completion" on a bridge defined as a HOST.
Does this mean there is an additional constant or two in the bench directory
that have to be manipulated, or that there is a special run of SYSTEM other
then"

    "restart -f"
    "run -a"

Perhaps one of my real areas of non-comprehension is the implication of
defining this as a HOST versus GUEST bridge. In the actual hardware I am
designing, I will be loading this bridge (be it HOST or GUEST, I don't know
which yet) into a VirtexE. Then, building a small board to provide a PCI
interface connector to a PCI ad-on card that contains an interface that
normally plugs into a PC. This means that I have to provide PCICLK, RST,
arbitration, and deal with IDSEL issues (we can forget about the INTA issue,
as I have a way around as long as I can allow either the PCI-WB bridge or my
board to be a master and perform memory writes/reads across the PCI bus.

On the RAMB4_S16_S16, I did spend some time yesterday updating the Modelsim
libraries so they can at least find the RAMB4 module as defined in the
PCI-WB bridge files wb_tpram.v and pci_tpram.v, but when I try to load the
simulation, I get an unresolved reference to glbl in GSR.glbl. I did then
follow the ap note at Xilinx regarding adding glbl.v to the project and
recompiling so the GSR (GlobalSetReset) signal was resolved to no avail. So
until I can understand that one, I am forced to try to work the simulation
with just generic RAM defined as I try to get to my next level of
understanding with the bridge code.

p.s. We can certainly carry on a private conversation, but I am suspecting
that some of the issues we might discuss here might help others along their
path to understanding.

Charles Krinke
http://home.pacbell.net/cfk




----- Original Message -----
From: <ctc-dsl@pacbell.net>
To: <pci@opencores.org>
Sent: Friday, May 17, 2002 8:18 PM
Subject: Re: [pci] first day with Modelsim


> I recently managed to get Modelsim XE Starter 5.5e
> to run a GUEST simulation to completion in 30+
> hours by making the following changes in two files.
>
> In system.v -- comment out lines 862 & 864-866
> If you don't, you'll find pci_tb.log stops growing
> during the first hour or so as a two-word read
> is retried over and over and over.
>
> In pci_user_constants.v
>   -- uncomment line 66 (FPGA)
>   -- uncomment line 67 (XILINX)
>   -- uncomment line 95 (GUEST)
>   -- comment line 96 (HOST)
>
> My pci_tb.log for the run ends saying
> Tests performed: 27,700
> Failed tests: 0
> Successful tests: 27,700
>
> If you need more details,
> you may contact me directly
> at ctc-dsl@pacbell.net
>
> Bill Siegmund
> Cal-Tex Computers, Inc.
>
> P.S.
> You should have a copy of
> RAMB4_S16_S16.v in your
> Xilinx\verilog\src\unisims
> directory.
> --
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