RE: [pci] burst data phase.

["Tadej" <tadej@opencores.org>]

Hi all!

First I must say, that FRAME# signal must be INACTIVE with last data,
nometer if it is burst or single, whil IRDY# signal must be asserted when
data is transfered (off course with TRDY# and DEVSEL#).
FRAME# signal is used to indicate the address phase when it is active, and
last data phase when it is inactive, with IRDY# asserted.

Regards,
	Tadej

-----Original Message-----
From: owner-pci@opencores.org [mailto:owner-pci@opencores.org]On Behalf Of
runner
Sent: Thursday, February 07, 2002 1:45 AM
To: pci@opencores.org
Subject: Re: [pci] burst data phase.


rama mohan£¬
	the master needn't to know how mang cycles to maintain. in single date
transfer mode, the FRAME#(driven by master) will maintain active until the
target asserts the TARRDY# or STOP#. That's to say FRAME# is driven active
when master need to get/receive data and deasserted when it finishes the
data phase.



>pci gurus,
>       I have devoleped pci 32 bit 33 mhz core with single data phase
>transaction facility only. I would like to add the burst data phases
>feature. I am devoleping that. But i strucked at one point.
>How master come to know that for how many clock cycles to maintain frame.
>Any body can give me suggestions.
>All kinds of suggestions are appreciated.
>
>thanks in advance
>
>ramu
>
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            runner
            runner@zh.t2-design.com

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