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Tadej,
Hi again.
Things are going ok - I have a simple target
integrated into a simulation model.
However, It is hard to write generic vhdl (i.e. not
instantiate xilinx specific stuff) or rloc's and still make 66mhz timing in a
Virtex-e.
I am being sent on a 2 week business trip, so
progress will be slow for a bit - however I hope to check in a first
attempt when I get back.
Cheers,
Mike.
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