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2. I call that module that writes frames to the memory, sets
the DMA and Ethernet registers host. It can be a processor, some kind of state
machine, etc.
The
destination address should be mac's address. That means that addresses [31:12]
must select the MAC, while [11:10] select the buffer within the mac.
assign RegCs = wb_stb_i & wb_cyc_i &
DWord & ~wb_adr_i[11] & ~wb_adr_i[10];
assign BDCs = wb_stb_i
& wb_cyc_i & DWord & ~wb_adr_i[11] &
wb_adr_i[10];
From
here you can see that when wb_adr_i[11] and wb_adr_i[10] are both 1 then
buffer is selected.
3.
Destination field remains the same always. This is MAC
address.
7.
When you write DMA buffer descriptor, you must also write the MAC buffer
descriptor. When the descriptor is set as READY, the DMA request is set
automatically.
Regards,
Igor
Hi Igor,
I have some doubts regarding buffer
descriptors. I am giving the sequence of operations what I am following
(for transmission).
1. Storing the data in the memory.
2. Writing the buffer descriptor with the source
address pointing to location where the data is stored. (Which address
should I mention in the destination address field? Specification for the Ethernet IP Core specifies
to write with the Ethernet Host interface-What is it mean?)
3. Setting the bits INC_SRC, INC_DSR,
SRC_SEL, DES_SEL and EOL to high.
4. Next Pointer field with next buffer
descriptor.
5. Enable channel.
6. Set the bits TXEN and DMAEN bits to
high.
7. Assert the REQ0 signal.
How the source address and destination addresses
are incremented if I set the respective bits? Where the Channel registers are stored? If they are stored
outside the Ethernet IP Core, how these will be controlled? If I am
interfacing this IP Core to any processor, how the processor will
controls channel registers?
Waiting for the reply.
Regards,
Veeresh
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