Re: [ethmac] expecting help

Hi Igor,

Thanks for the reply. I am facing one more problem in understanding eth_wishbonedma.v module. EOL and CH_EN bits are not described in specification document. Is there any register to describe these bits? If I store frame in the external memory, how can I point the location of the frame stored? Please clarify me.

Regds,

Veeresh

----- Original Message -----

From: Igor Mohor

To: ethmac@opencores.org

Sent: Wednesday, December 05, 2001 3:09 PM

Subject: RE: [ethmac] expecting help

Yes, you're right.

First of all I have to tell you that buffer descriptors (256 BD totally) arelocated internally in the

eth. MAC.

If you take a look in the eth_top.v file, you'll find this:

assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10];
assign BDCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & wb_adr_i[10];

Transmit buffer descriptor addresses are fixed to address where: ~wb_adr_i[11] & wb_adr_i[10]

This means that Buffer descriptors might be between 0x400 and 0x800.

RX_BDBASE_ADDR is deleted (don't exists any more). RX_BD_NUM is new and tells you how

many buffer descriptors are used for RX BD. If you write value 0x80 to this register

that means that 128 BD are used for Rx BD while the rest 128 are used for Tx BD.

In this case you have:

0x400 to 0x5FC Tx BD

0x600 to 0x7FC Rx BD

TX_STATUSn and RX_STATUSn registers don't exist any more. Status is written back to the

buffer descriptors and are avaliable from the addresses mentioned above.

Regards,

    Igor

-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of Veeresh
Sent: 5. februar 2001 8:59
To: ethmac@opencores.org
Subject: Re: [ethmac] expecting help

Hi Igor,

      While going through the updated specifications, I found that some of the registers were not included from the old one (updated on 03.07.01). Please clarify me.

      The registers which are not included are given below,

1. TX_BDBASE_ADDR (Transmit BD Base Address Reg)

2. TX_STATUSn (Transmit Status Register n)

3. RX_STATUSn (Receive Status Register n)

Thanking you.

Rgds,

Veeresh

----- Original Message -----

From: Igor Mohor

To: ethmac@opencores.org

Sent: Wednesday, December 05, 2001 12:34 PM

Subject: RE: [ethmac] expecting help

Sure,

many people is doing the same thing. Feel free to ask what you need to know.

Regards,

    Igor

-----Original Message-----
From: owner-ethmac@opencores.org [mailto:owner-ethmac@opencores.org]On Behalf Of Veeresh
Sent: 5. februar 2001 7:32
To: ethmac@opencores.org
Subject: [ethmac] expecting help

Hi all,

     I am Veeresh, working as Hardware Design Engineer. I am trying to implement the Ethernet MAC (from Opencores) on the FPGA. Please help me to do this.

Thanks.

Regards,

Veeresh