[ethmac] RE: Status of Open Ethernet MAC Core / Eventual Contribution

["Igor Mohor (uni-mb)" <igor.mohor@uni-mb.si>]

Hi, Raymund.

Sorry for the late reply, I was out of town. It would be great if you
could help us building the eth MAC. You can start by reading my comments
below :)

> -----Original Message-----
> From: Raymund Hofmann [mailto:rhofmann@raygmbh.de]
> Sent: 24. april 2001 13:00
> To: igorm@opencores.org
> Subject: Status of Open Ethernet MAC Core / Eventual Contribution
>
>
> Hi,
>
> I have quickly viewed all Information about the Ethernet Core on
> opencores.org.
> As i see it, some verilog modules are finished, but most of it
> still has to
> be done.
> Also some concepts do not seem to be finished.
> As i understood the MAC is supposed to read descriptors via DMA over the
> Wishbone interface, but i could not understand how with the existing
> definition of the Wishbone Interface in the doc it should apply a
> address to
> read the Descriptor's (and read/write data blocks).

The DMA and the buffer descriptor logic both changed. Don't worry about
that. I'll update the ethernet MAC core spec. within few days. And the
update also includes the host interface with the descriptors and DMA.


> As i would like to have a minimalistic Ethernet MAC for a embedded system
> FPGA, i could also contribute something to this Project.
> Unfortunately my Experience related to Ehternet is very limited.
> I designed a few FPGA's and a 200K Stdcell Asic (Video related)
> with Verilog
> (Synopsys / Verilog XL).
> What do you think will be the Proceeding of the Ethernet Project ?
> Could i contribute some useful work, despite my lack of Ethernet
> experience
> ?

Sure. We are all here to learn :)

The current status is:
- Rx module is finished by Mahmud. I just try it a bit but I didn't really
test it. I don't know if he's improving the core or that is the final
version. We need his answer about that. Somebody also needs to spent more
time on testing the core.

- Tx module is finished by Novan. He unfortunatelly left the team because if
his work and some other reasons. Thanks, Novan.
This core also needs to be tested.

- MAC Control module. Nothing has been done so far.

- MII Management module: I finished it and test it. I also posted the test
bench program on the net. So far I'm satisfied with it. For double check
somebody should spend some time in testing it.

- Host interface with the buffer descriptors and DMA: Nothing done, yet. I
would like to do it, since I'm good contact with the RISC and DMA
developers.

- Ethernet specification update is in progress. I'll finish that in short
time. I already promised that but I was working on some other things, too.

It would be great to know what kind of tools you guys use. You can also send
me a direct reply. Some tools is possible to get as a opencores developer.
Check the webpage.

Illan Glasner seems to have a lot of experiance with the eth mac. It would
be really great if he could help with advices. I would be specifically happy
on guidelines on how to test the cores (detailed guidlines would be
prefered).

I know that all of us are busy with doing something and nobody can push
anybody else but in order to finish things in some finite period of time I
would like all of you to allowe me to ask you about the status time to time.
If that is acceptable with everybody, that is great, if not, give me your
ideas.

Our goal is to have a working version in FPGA in 8 weeks from now.



Regards,
	Igor


>
> best regards
> Raymund Hofmann
>
> RAY Electronic-Design GmbH
> Lagerstrasse 49
> 64807 Dieburg, Germany
> Tel ++49 6071-986000
> Fax ++49 6071-9860098
>
>