[oc] I2C Master Core problem

["matija habek" <mhabek@net.hr>]

Hello.
I have problems with sending data via I2C Master Core.Can somebody tell me,

which registers must I initialise and which bit's in register's too, every step

please.
Which Wishbone signal mus I assert?How many clock cycles must I use for initialisation

registers?Can somebody send me a example of SCF Wavewform file for simulation

in VHDL if thats not a problem?
Thanks.
Regards,Matija from Croatia


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