??: [oc] AMBA - SDR/DDR SDRAM controller

["Zhichong Chen (Beijing)" <ZhichongChen@viatech.com.cn>]

hi, rudi

I have a question. Since AHB uses only rising edge and DDR using both 
clock edge, is that means the frequency of HCLK is at least 2x frequency 
of DDR clock?

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On Wednesday 20 November 2002 10:13, Srikant Cheruvu wrote:
> I was looking through the list of pending projects on the site and
> noticed a common interface from AMBA to SDR/DDR SDRAM. I'm looking into
> doing something similar as well, and I wanted to get some suggestions
> as to how to proceed. First off, is this even possible, ie, efficient?

I think it's very possible and efficient as well. When I looked at it,
I though it should quite straight forward. For DDR, you use both clock
edges to sample data (hence double data rate) for SDR only the rising
edge. This is a VERY simplified view, and there is some additional logic
required to support DDR. Mostly the complexity lies in keeping the
data path clean to allow it to handle double data rate.


> How are the different timing requirements to the two kinds of memories
> handled? Should there be some kind of muxing involved as far as the
> control signals go? And how are DDR-specific control signals such as
> DQS handled? I don't want too many low-level details..just an answer on
> whether it'll be possible, efficient, and some high-level design
> suggestions would be very helpful.

I personally don't like muxing control signals if possible. You should
try to handle all casesin your state machine, and change the way the
control work depending on the memory type ...

>
> thanks,
> sc


rudi
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