[oc] AMBA - SDR/DDR SDRAM controller

[Srikant Cheruvu <azeroth99@yahoo.com>]

I was looking through the list of pending projects on the site and
noticed a common interface from AMBA to SDR/DDR SDRAM. I'm looking into
doing something similar as well, and I wanted to get some suggestions
as to how to proceed. First off, is this even possible, ie, efficient?
How are the different timing requirements to the two kinds of memories
handled? Should there be some kind of muxing involved as far as the
control signals go? And how are DDR-specific control signals such as
DQS handled? I don't want too many low-level details..just an answer on
whether it'll be possible, efficient, and some high-level design
suggestions would be very helpful.

thanks,
sc

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