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Re: [oc] New! FFT core
hi,
I have been really struggling with the fft code and have not been able to
use it right, mainly because I really don't know much of the fft algorithm
and am also a kind of novice in VHDL. Could you or someone pls help me out
with this one? I have been using Modelsim for presynth simulation and have
synopsys tools. I have tried to write a test bench which I have pasted
below. I had to make certain modifications to your files so that they would
compile with modelsim and also had to change the blockram portion with the
appropriate one for synopsys. Initially when I ran the testbench I got some
output results. But they weren't right as outdataen signal never went high.
But all the data did get written into the ram and were being read out of the
ram correctly. I ran the simulation for 50000ns and used cfft1024x12 as is
in the imp folder.
The test bench..
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
entity tb_cfft1024x12 is
end tb_cfft1024x12;
architecture tb of tb_cfft1024x12 is
component cfft1024X12
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
inv : in std_logic;
Iin : in STD_LOGIC_VECTOR(11 downto 0);
Qin : in STD_LOGIC_VECTOR(11 downto 0);
inputbusy : out STD_LOGIC;
outdataen : out STD_LOGIC;
Iout : out STD_LOGIC_VECTOR(13 downto 0);
Qout : out STD_LOGIC_VECTOR(13 downto 0)
);
end component;
signal clk : STD_LOGIC;
signal rst : STD_LOGIC;
signal start : STD_LOGIC;
signal inv : std_logic;
signal Iin : STD_LOGIC_VECTOR(11 downto 0);
signal Qin : STD_LOGIC_VECTOR(11 downto 0);
signal inputbusy : STD_LOGIC;
signal outdataen : STD_LOGIC;
signal Iout : STD_LOGIC_VECTOR(13 downto 0);
signal Qout : STD_LOGIC_VECTOR(13 downto 0);
signal Io : STD_LOGIC_VECTOR(13 downto 0);
signal Qo : STD_LOGIC_VECTOR(13 downto 0);
begin
f: cfft1024x12 port map(clk=>clk,
rst =>rst,
start=> start,
inv=>inv,
Iin=>Iin,
Qin=>Qin,
inputbusy=>inputbusy,
outdataen=>outdataen,
Iout=>Iout,
Qout=>Qout);
-- to adjust the output sequence
Io(0)<=Iout(12);
Io(1)<=Iout(13);
Io(2)<=Iout(10);
Io(3)<=Iout(11);
Io(4)<=Iout(8);
Io(5)<=Iout(9);
Io(6)<=Iout(6);
Io(7)<=Iout(7);
Io(8)<=Iout(4);
Io(9)<=Iout(5);
Io(10)<=Iout(2);
Io(11)<=Iout(3);
Io(12)<=Iout(0);
Io(13)<=Iout(1);
Qo(0)<=Qout(12);
Qo(1)<=Qout(13);
Qo(2)<=Qout(10);
Qo(3)<=Qout(11);
Qo(4)<=Qout(8);
Qo(5)<=Qout(9);
Qo(6)<=Qout(6);
Qo(7)<=Qout(7);
Qo(8)<=Qout(4);
Qo(9)<=Qout(5);
Qo(10)<=Qout(2);
Qo(11)<=Qout(3);
Qo(12)<=Qout(0);
Qo(13)<=Qout(1);
clockgen: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
process
file FileIn1 : text is in "bindata"; -- bindata file contains 1 to 1024 in
binary
variable LineIn1 : line;
variable InputTmp1 :std_logic_vector(11 downto 0);
variable feed : integer:=1;
begin
if feed=1 then
rst<='1';
wait until clk'EVENT and clk='1';
rst<='0';
wait until clk'EVENT and clk='1';
inv<='0';
start<='1';
wait until clk'EVENT and clk='1';
start<='0';
Qin<="000000000000";
while not( endfile( FileIn1)) loop
readline( FileIn1, LineIn1);
read(LineIn1, InputTmp1);
Iin<=InputTmp1;
wait until clk'EVENT and clk='1';
end loop;
feed:=0;
end if;
end process;
end tb;
----- Original Message -----
From: <sradio@opencores.org>
To: <cores@opencores.org>
Sent: Tuesday, November 19, 2002 3:59 AM
Subject: Re: [oc] New! FFT core
> For circuit simplification, the CFFT output order is not bit reversed but
> radix 4 reverse ordered. For example,
>
> c is the signal of output step counter,
> a is the signal of output order,
> If the CFFT is 1024 points,
>
> a(9 downto 0)<=c(1 downto 0)&c(3 downto 2)&c(5 downto 4)&c(7
> downto 6)&c(9 downto 8);
>
> (:
>
>
>
> ----- Original Message -----
> From: John Dalton <john.dalton@b... >
> To: cores@o...
> Date: Mon, 18 Nov 2002 03:00:52 +1100
> Subject: Re: [oc] New! FFT core
>
> >
> >
> > > After me, may be John can can do a final round of editing ?
> > ;*)
> >
> > Did someone say my name? Does 'John' refer to me?
> >
> > If so, I don't mind doing an edit. My FFT core has been at a stand
> > still
> > for ages now, so if I can make a contribution by doing some
> > editing, I'm glad to.
> >
> > A corrected version of the text from the document cfft/cfft_e.pdf
> > is appended to this email.
> >
> > Regards
> > John
> >
> > --------------------
> >
> > 1. Description
> >
> > CFFT is a radix-4 fast Fourier transform (FFT) core with
> > configurable data width and
> > a configurable number of sample points in the FFT.
> >
> > Twiddle factors are implemented using the CORDIC algorithm,
> causing
> > the gain of the
> > CFFT core to be different from the standard FFT algorithm. This
> > variation in gain
> > is not important for orthogonal frequency division modulation
> > (OFDM) and demodulation.
> > The gain can be corrected, to that of a conventional FFT, by
> > applying a constant
> > multiplying factor. The input to the FFT is naturally ordered
> > {editor's note: have I
> > interpreted this correctly?} while the output of the FFT is bit
> > reversed,
> >
> > 2. Theory of Operation
> >
> > The reader is referred to one of the many explanations given in
> > common textbooks.
> > {editor's note: provide reference}
> >
> > 3. Block Diagram
> >
> > 4. Timing
> >
> > 5. Miscellaneous
> >
> > a. Gain
> >
> > Points Standard FFT CFFT Standard IFFT CFFT(inverse)
> > 256 1 0.0698 1/256 17.9
> > 1024 1 0.0287 1/1024 29.4
> > 4096 1 0.0118 1/4096 48.2742
> >
> > b. Output Order
> >
> > The output sequence is bit reversed. For example, the 789th
> > (1100010101(base 2)) output
> > of a 1024 point FFT corresponds to a normalised frequency of
> > 675/1024 (1010100011(base 2)).
> >
> > c. Synthesis
> >
> > This core can be synthesized using Synplify70. It can be placed
> > and routed using Xilinx ISE4.1.
> > A 1024 point FFT, with a 12 bit I/Q input can be fitted into an
> > XCV50E-6 and runs at a
> > clock speed of 90MHz.
> >
> --
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>
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