Re: [oc] Open Core Forth Processor

[John Griessen <john_g@cibolo.com>]

On Mon, 2002-10-28 at 03:11, John Sheahan wrote:
> On Mon, Oct 28, 2002 at 03:21:13AM -0100, j-p.martin@laposte.net wrote:
> > > -- This code represents my current thoughts on designing a Forth 
> > > Processor in VHDL. 
> 
> Wow. phoenexis from a distant past.
> 
> why not verilog (ducking)
[jg]Sure, both.  VHDL for specifying, and icarus verilog and open source
jeda language for testbenches. 


> is external memory required?  internal ram would be an interesting 
> option here
[jg]The fpga companies all seem to have memory as a base now..  So using
the internal locally available memory makes sense for most projects.  I
like the idea of using forth on fpga as an OS for reconfiguring DSP
datastreams once a dictionary of such functions in the specific setting
is developed.   This kind  of forth should definitely have program and
data addressable just as easily -- so it can be an interactive forth
once the fpga "hardware" is set and dictionary is replete with functions
you like.  If you want to lock it down, I'm not sure how to do it with
fpgas anyway...for instance if they load from an outside config memory,
encrypt the main one of those, and have a feature of the fpga decrypt
that with a key from a rom burned into it or flash rom previously loaded
in it...security will depend on fpga features...

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