Re: [oc] Open Core Forth Processor

[John Sheahan <jrsheahan@optushome.com.au>]

On Mon, Oct 28, 2002 at 03:21:13AM -0100, j-p.martin@laposte.net wrote:
> > -- This code represents my current thoughts on designing a Forth 
> > Processor in VHDL. 

Wow. phoenexis from a distant past.

why not verilog (ducking)

> > 
> > -- If it could fit into a Xilinx 4005 or 4010 it would be ideal! 

isn't the 4000 series effectively obselete?
why not consider optimizing for a virtex or an altera equivilant.


whats the architectural model here?
looks like code and data are coincident

data and return stacks are separate and on-chip ?

is so - why so small?   and why not paramterized?
only a tiny fracion of the forth I have written would fit in these.
multitaskers for example could swap stack pages in the NC4000.

Any thoughts on the testbench architecture planned? 
Starting with cmforth and tweaking that for the final rtl/instruction
set  could  be a plan. 

> > 
> > -- should be limited to the external RAM speed when memory access 
> > is required. 

is external memory required?  internal ram would be an interesting 
option here

> > 
> > -- 16 bit data bus (to save space, could be 8 bit but it would take 
> > more statements) 
> > 
> > -- 16 bit address bus 

the intrinsic data width and the address space should probably be the
same.  The implemented saddress space might be less.
 
the data bus could perhaps be narrower,  but then you have to add 
byte type accesses. ugg.

john
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