RE: [oc] ALDEC Vs. ModelSIM (VHDL Simulator)

["Paul McFeeters" <paul.mcfeeters@ntlworld.com>]

Frederic,

I personally use Webpack 4.1 which is quite happy to invoke Model Sim and
simulate my designs. Hope it helps.

Paul

> -----Original Message-----
> From: owner-cores@opencores.org [mailto:owner-cores@opencores.org]On
> Behalf Of Frederic
> Sent: 08 February 2002 19:00
> To: cores@opencores.org
> Subject: Re: [oc] ALDEC Vs. ModelSIM (VHDL Simulator)
> 
> 
> Gentlemen,
>     Can Model Sim be launched from Xilinx Foundations 3.1i? I cannot find
> out how to simulate RTL benches in Xilinx Foundations 3.1i? The Xilinx tool
> always tell me that some of testbench featues in Verilog/VHDL are not
> supported and it seems accept testbenches written in *.cmd only. Maybe I am
> wrong, but I would be very appreciative of you learned gentlemen's comments.
> 
> Frederic Chen
> 
> ----- Original Message -----
> From: <Billditt@aol.com>
> To: <cores@opencores.org>
> Sent: Saturday, February 09, 2002 12:16 AM
> Subject: Re: [oc] ALDEC Vs. ModelSIM (VHDL Simulator)
> 
> 
> > I have used Model Sim VHDL sim.
> >   It was a good simulator. In fact, Model Sim came out with VHDL
> > sim first. It wasnt till much later that Verilog sim came out.
> > They also have a mixed mode (Verilog and VHDL). I havent
> > used that.
> >         ditt
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