Re: [oc] Driving a RS232 serial port semi-direct from the FPGA?

["Damjan Lampret" <lampret@opencores.org>]

Paul,

might this could be of help to you:

http://www.opencores.org/projects/rs232_syscon/

regards,
Damjan

----- Original Message -----
From: "Paul McFeeters" <paul.mcfeeters@ntlworld.com>
To: <cores@opencores.org>
Sent: Friday, January 11, 2002 2:20 PM
Subject: [oc] Driving a RS232 serial port semi-direct from the FPGA?


> Hi all,
>
> I need a bit of advice on RS232 ports.
>
> As my board is designed to run Linux its a given that I need to have a
serial port on it.
> I already have a parallel port on it which works great so I thought a
serial port will be
> even simpler to do (if thats possible).
>
> Alas it seems more like a minefield, obviously the first thing was to look
at the UART16550
> core on opencores to see what I can learn from that and maybe make use of
it. Unfortunately
> Jacob's project fusses over registers and higher level stuff than I need,
all I want is a
> very simple port for people to run up a console program via a PC's comms
program and talk
> to the FPGA. My first design doesn't even bother with any form of hardware
handshaking.
>
> I've found a good site which explained the null modem cable for PC to PC
style communication.
> Then I bought a MAX233CPP RS232 driver chip to handle the conversion
from/to 5V TTL to the
> RS232 +10v/-10v signal levels. Thus my current plan looks like this:
>
> FPGA                     My board                        PC side
>                           D9 plug                        D9 plug
> FPGA GND ---------------- P5 GND--------------------------GND P5
> FPGA Px --- MAX233CPP --- P3 TD----------------------------RD P2
> FPGA Py --- MAX233CPP --- P2 RD----------------------------TD P3
>
>                           P1 CD----|                  |----CD P1
>                           P4 DTR---|                  |---DTR P4
>                           P6 DSR---|                  |---DSR P6
>
>                           P7 RTS--|                    |--RTS P7
>                           P8 CTS--|                    |--CTS P8
>
> CD->DTR->DSR, RTS->CTS, to bypass hardware handshaking at the moment.
>
> I just need my port to do the standard 9600N81 (9600 baud, No Parity, 8
Data Bits and 1 stop bit),
> later on can adjust it. As far as I understand the serial-wire standard
this is what happens:
>
> TD is asserted (high 1) until some data is ready to go.
> TD is negated for 1 clock cycle (this is the 'start' bit)
> TD then transmits the eight data bits sequentially (bits 0->7 in that
order I believe)
> TD is either asserted to signify the 'stop' bit or is negated which means
its actually the
> start bit for another eight data bits
>
> Thats about all my understanding of the workings of the serial port so
far. I've got to connect
> up my MAX233CPP chip later and try out my limited knowledge to test it. So
if anybody has some
> pearls of wisdom for me feel free to email me.
>
> Paul
> "A FPGA programmer's work is never done"
>
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