Re: [oc] A 'core server' ?

[Tomas Bautista <bautista@cma.ulpgc.es>]

On Oct 30 2001 15:53, Jecel Assumpcao Jr <jecel@merlintec.com> wrote:

> Would IDaSS help?
>
>   http://www.ics.ele.tue.nl/~averschu/idass.html
>
> It can generate both VHDL and Verilog from the same high level design.

It certainly helps, but... you have to learn a new language (although it is 
not difficult), you use a new --not complicated-- tool, you can generate VHDL 
and Verilog (currently VHDL for Compass if I'm not wrong and Verilog for 
Xilinx tools, although the way that is generated is configure through 
template files with its own syntax, of course) and there are some things 
which cannot be directly designed.

But for most digital designs related with microprocessors and similar... it 
suits pretty fine. We are using it in our school for years till now :-)

Greetings,

  Tomás.

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