[oc]:Help on Backend Verification

[khong lin pang <mailtopang@yahoo.com>]

Hi all,

This is my first posting to the list, please point out
any errors like wrong tagging or subject. I am
extremely fresh in this area but i am forced to
continue ( alone ) a project started by a group of
people. I had no prior training in Synopsys or
Verilog, but i have tried learning up Verilog for the
past one month. If there are any active list for
beginner and desperate people like me, please tell me.

The problem -

- This project is basically a microcontroller, with a
8051 core and some others component like serialX,
watchdog, real time clock, and general purpose IO.
- The verilog coding was finished some time ago and
test bench was written to test each component and the
whole controller as well. It tested good. ( Is this
what you call front end design and front end
verification? )
- Now the net list was generated and it was send to
another vendor for layout purposes. The vendor return
two netlist files, one is the sdf and the other...
timing file?
- Now we are suppose to verify again on the return
file to see if it is correct.( Is this call backend
verification? ) But the problem is how are we going to
change our test bench when all the naming conventions
has changed? Usually what should be done to be able to
test it again?

- I am running out of time, but nobody seems to care,
those engineers that help to develope the system has
other project to handle and i guess when the deadline
comes i will be the person that everyone point their
fingers to. Please help.


Rgds,

Dmm


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