Re: [oc] serial UART in cadence

["Guoqing Zhang" <gxz0233@hotmail.com>]

well. for "import verilog(Vhdl)  " in cadence. you need a std library for 
mapping your hdl netlist to cadeence schematic. for example. your should 
have a nand2 symbol in your cadence map_lib to map a nand2 gate which in hdl 
netlist.if you don't have the std lib, all modules(like nand2) in hdl 
netlist will map to a functional cellview in cadence library.

ps. hdl netlist should be in gate level.

actually I don't understand why you need to import vhdl to create schematic. 
you can do simulation from prompt.

good luck

Guoqing Zhang


>From: Eric Thompson <thompe2@rpi.edu>
>Reply-To: cores@opencores.org
>To: cores@opencores.org
>Subject: [oc] serial UART in cadence
>Date: Tue, 27 Feb 2001 16:56:57 -0500
>
>hi-
>     I would like to try to do a simulation of the serial UART leading to
>interfacing it with some other open cores for a class project on
>core-based design.
>     I do not have access to modelSim which i see the UART was originally
>simulated with.  I do have access to cadence.  Does anyone know what it
>would take to import this uart in cadence?  If i do "import vhdl" now it
>complains that there is no std library.
>is it named something different in cadence?  i have basic, analog, and a
>bunch of others.
>i'm rusty on vhdl so any help would be greatly appreciated.  thanks.
>This project would also lead to at least my contributing to any cores we
>use if possible.  The other students may also contribute as the project
>moves ahead.
>             thanks-
>                 eric thompson
>

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