Re: [openrisc] Instruction Fetch

["Damjan Lampret" <lampret@opencores.org>]

Heya !

I'm not sure what you mean exactly but I'll tell you the following. For
example the code is being executed from an instruction cache, and if there
is an instruction cache miss, the pipeline will continue to execute
instructions regardless it is waiting for instruction cache to complete the
cache line and start deliverting instructions to the pipeline. That means
while instruction cache is not delivering instructions, pipeline is feed by
NOPs.

regards,
Damjan

----- Original Message ----- 
From: "#KUGAN VIVEKANANDARAJAH#" <kugan@pmail.ntu.edu.sg>
To: <openrisc@opencores.org>
Sent: Thursday, August 21, 2003 11:59 AM
Subject: [openrisc] Instruction Fetch


>
> Hi again,
> I am simulating the orp_soc to see the instruction fetch architecture.
> It seems that instruction fetch is being stalled alternate clk cycle and
> a NOP instruction is added by or1200_if. Is it because some thing is
> wrong with my or1200_defines ? Or is there any reason for this.
>
> Am I miss understanding it completely?
>
> Thanks in advance,
> Kuagn
>
>
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