RE: [openrisc] Success!

["Brian Adams" <brian.adams@annapmicro.com>]

All,

  We were getting the same thing when we tried uCLinux out here.
(running CPU and SRAM at 30Mhz)  It did turn out to be the timer.  In
the default include/ams-or32/system.h SYS_TICK_PER is set to 0x10000.
If I understand it correctly, this is programmed into the tick timer to
generate an interrupt every time it counts from SYS_TICK_PER to 0.  Each
interrupt constitutes 1 CPU 'tick'. (don't really know what to call it)
Anyway, there are 100 'ticks' per second. (because HZ is defined to be
100 in include/asm-or32/param.h(?))  So you have to calculate
SYS_TICK_PER so the timing works out correctly.  Basically I guess it
is...

   SYS_TICK_PER=<CPU Frequency>/HZ

  Setting it correctly for my frequency 30Mhz, (without cache) made the
MIPS go from 0.81 (which is the minimum allowed by the algorithm, I
think) to 2.4ish.  When I enable to cache it jumps to 14.89. (But then
promptly hangs, bummer.  I'll be looking at that today.)

  You probably all knew this already, but I have been working on
figuring this very thing out over the past couple days, so I thought I
would share for the uCLinux impaired like myself.

Brian 

-----Original Message-----
From: owner-openrisc@opencores.org [mailto:owner-openrisc@opencores.org]
On Behalf Of Damjan Lampret
Sent: Friday, August 08, 2003 6:00 AM
To: openrisc@opencores.org
Subject: Re: [openrisc] Success!

So far nobody seriously looked at the bogomips, I think it gets
calculated
incorrectly (at 25MHz with caches enabled it says something like 2
bogomips
which is kind of stupid ...). Probably somebody would have to check the
timer...

regards,
Damjan

----- Original Message ----- 
From: "Damon Brantley" <brantley@mcloudteleco.com>
To: <openrisc@opencores.org>
Sent: Friday, August 08, 2003 7:16 AM
Subject: [openrisc] Success!


> Just thought I would let everyone know that I have finally gotten
uClinux
> to run on my Digilent board with a 300K Spartan. I did have to build
an 8M
> DRAM board since the Digilent board does not have any memory.
> Basically I have synthesized the openrisc cpu with no cache, no
> multiplier, the uart 16550, a trimmed down traffic cop and an sdram
> controller that I wrote. Gate utilization is currently at 95%
according to
> xst, but I think there are a few unused bits and pieces I can remove
to
get
> the utilization below 90%.
> The cpu is clocking at 25Mhz and the dram at 50Mhz. The BogoMips are
at
> .81 which is pretty abysmal, but the slowness is due to the  dram
> controller. I wrote it for simplicity rather than efficiency.
> If there is interest I can organize and post my work into cvs.
> This configuration will not operate standalone, but if someone wanted
a
> low budget way to experiment with uclinux on openrisc, it is possible.
>
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