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[cvs-checkins] ethernet/rtl/verilog eth_defines.v eth_spram_2 ...

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] ethernet/rtl/verilog eth_defines.v eth_spram_2 ...
From: OpenCores CVS Agent <cvs@www.opencores.org>
Date: Thu, 14 Aug 2003 18:43:23 +0200
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	simons	03/08/14 18:43:22

Modified files:
	rtl/verilog    : eth_defines.v eth_spram_256x32.v 

Log message:
	Artisan ram instance added.

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