Re: [usb] question about the DLL in the UTMI

["Luis J. Perez" <luis.perez@ds2.es>]

Jiang daosan wrote:
> 
>  Hi, Luis:
> 
>      Thank you so much for your answer.  However, I think there maybe something
> to talk about more, As you written:
> >To design a HS PLL you need an external clock of 480x4 MHz (at least, I
> >think) to obtain the data signal synchronized with the internally
> >extracted 480 MHz clock.
> I was wonder that there is some mistake? As the external clock of 480x4 MHz is
> so high, it may be impossibe in practice. I saw the needed external clock in
> Phlips ISP1501 is 12MHz. In my opinion, the internal local 480MHz clock is
> produced by the Clock Multiplier with the external 12MHz Clock in the UTM,
> And then it was made some Phase delay by the HS DLL to synchronized to the clock of
> the incoming data. That delayed Clock is the exacted clock. Am I right ?
> 

Yes, sorry, I was thinking on my design...

The delayed clock you are referring is the extracted clock (480 MHz
one). But, how to 
design in HDL a Digital PLL for HS? I don't know another way of
syncronizing both clocks (internal and the incoming data one) than
sampling the incoming data with a quicker clock. Any other idea?


========================================================
Luis Jose Perez Lafuente      	luis.perez@ds2.es
Design Engineer
Digital Design Department

Design of Systems on Silicon  	http://www.ds2.es
Av. Charles Robert Darwin, 2  	Phone.  +34-96-136 60 04
Parc Tecnologic	              	                Ext. 152
46980 Paterna (VALENCIA)      	FAX     +34-96-136 62 50
SPAIN
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