Re: [pci] pci board layout specifications

[mlange@ieee.org]

Marco,
 
 I laid out a double layer PCI board, and it works fairly well. The clock 
line length has to be 2.5 inches (+- 0.1 inch), and you have to keep the 
other bus lines as short as possible. To be rigorous: the PCI spec states 
that the lengths of the bus lines (except for the CLK signal) have to be 
no longer than 2 inches. (!!)

 Another thing: the spec states that the PCI device, (the FPGA IC) has 
to have an input capacitance of 10pf per pin (max). I laid out my board 
using an older XC4k part, PLCC84, fitted in a socket that translates the 
pins to PGA84. In theory, all of that would add too much capacitance to 
the pins of the FPGA (as seen from the bus). Using a Spartan part, you 
will not have this problem.
 
Good luck with your thesis!

Mauricio Lange

----- Original Message ----- 
From: Marco Buffa <marcobuffa@l... > 
To: pci@o...  
Date: Fri, 17 Jan 2003 15:19:29 +0100 
Subject: [pci] pci board layout specifications 

> 
> 
> Good morning, 
> I'm going to prototipe a PCI board with the PCI-bridge core on a 
> Spartan 
> 2e for my thesis work. 
> I would like to know if there is some particular layout 
> specification 
> for the PCI signals (wire lenght, wire distance, low-R, ecc...) 
> 
> Thank's! 
> -- 
> Marco (Politecnico di Milano, Italy) 
> 
> "No, lo abbiamo esaminato dopo, e' perfetto. 
> Ma quando si ha paura si crede sempre che il motore vibri." 
> (Antoine de Saint-Exupery, "Volo di notte") 
> 
--
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